typedef union _WHEA_MEMORY_ERROR_SECTION_VALIDBITS {
struct {
ULONGLONG ErrorStatus :1;
ULONGLONG PhysicalAddress :1;
ULONGLONG PhysicalAddressMask :1;
ULONGLONG Node :1;
ULONGLONG Card :1;
ULONGLONG Module :1;
ULONGLONG Bank :1;
ULONGLONG Device :1;
ULONGLONG Row :1;
ULONGLONG Column :1;
ULONGLONG BitPosition :1;
ULONGLONG RequesterId :1;
ULONGLONG ResponderId :1;
ULONGLONG TargetId :1;
ULONGLONG ErrorType :1;
ULONGLONG Reserved :49;
};
ULONGLONG ValidBits;
} WHEA_MEMORY_ERROR_SECTION_VALIDBITS, *PWHEA_MEMORY_ERROR_SECTION_VALIDBITS;
typedef union _WHEA_ERROR_STATUS {
ULONGLONG ErrorStatus;
struct {
ULONGLONG Reserved1 :8;
ULONGLONG ErrorType :8;
ULONGLONG Address :1;
ULONGLONG Control :1;
ULONGLONG Data :1;
ULONGLONG Responder :1;
ULONGLONG Requester :1;
ULONGLONG FirstError :1;
ULONGLONG Overflow :1;
ULONGLONG Reserved2 :41;
};
} WHEA_ERROR_STATUS, *PWHEA_ERROR_STATUS;
typedef struct _WHEA_MEMORY_ERROR_SECTION {
WHEA_MEMORY_ERROR_SECTION_VALIDBITS ValidBits;
WHEA_ERROR_STATUS ErrorStatus;
ULONGLONG PhysicalAddress;
ULONGLONG PhysicalAddressMask;
USHORT Node;
USHORT Card;
USHORT Module;
USHORT Bank;
USHORT Device;
USHORT Row;
USHORT Column;
USHORT BitPosition;
ULONGLONG RequesterId;
ULONGLONG ResponderId;
ULONGLONG TargetId;
UCHAR ErrorType;
} WHEA_MEMORY_ERROR_SECTION, *PWHEA_MEMORY_ERROR_SECTION;
typedef union _WHEA_NMI_ERROR_SECTION_FLAGS {
struct {
ULONG HypervisorError:1;
ULONG Reserved:31;
};
ULONG AsULONG;
} WHEA_NMI_ERROR_SECTION_FLAGS, *PWHEA_NMI_ERROR_SECTION_FLAGS;
typedef struct _WHEA_NMI_ERROR_SECTION {
UCHAR Data[8];
WHEA_NMI_ERROR_SECTION_FLAGS Flags;
} WHEA_NMI_ERROR_SECTION, *PWHEA_NMI_ERROR_SECTION;
typedef union _WHEA_PCIEXPRESS_ERROR_SECTION_VALIDBITS {
struct {
ULONGLONG PortType :1;
ULONGLONG Version :1;
ULONGLONG CommandStatus :1;
ULONGLONG DeviceId :1;
ULONGLONG DeviceSerialNumber :1;
ULONGLONG BridgeControlStatus :1;
ULONGLONG ExpressCapability :1;
ULONGLONG AerInfo :1;
ULONGLONG Reserved :56;
};
ULONGLONG ValidBits;
} WHEA_PCIEXPRESS_ERROR_SECTION_VALIDBITS, *PWHEA_PCIEXPRESS_ERROR_SECTION_VALIDBITS;
typedef enum {
WheaPciExpressEndpoint = 0,
WheaPciExpressLegacyEndpoint,
WheaPciExpressRootPort = 4,
WheaPciExpressUpstreamSwitchPort,
WheaPciExpressDownstreamSwitchPort,
WheaPciExpressToPciXBridge,
WheaPciXToExpressBridge,
WheaPciExpressRootComplexIntegratedEndpoint,
WheaPciExpressRootComplexEventCollector
} WHEA_PCIEXPRESS_DEVICE_TYPE;
typedef union _WHEA_PCIEXPRESS_VERSION {
struct {
UCHAR MinorVersion;
UCHAR MajorVersion;
USHORT Reserved;
};
ULONG AsULONG;
} WHEA_PCIEXPRESS_VERSION, *PWHEA_PCIEXPRESS_VERSION;
typedef union _WHEA_PCIEXPRESS_COMMAND_STATUS {
struct {
USHORT Command;
USHORT Status;
};
ULONG AsULONG;
} WHEA_PCIEXPRESS_COMMAND_STATUS, *PWHEA_PCIEXPRESS_COMMAND_STATUS;
typedef struct _WHEA_PCIEXPRESS_DEVICE_ID {
USHORT VendorID;
USHORT DeviceID;
ULONG ClassCode:24;
ULONG FunctionNumber:8;
ULONG DeviceNumber:8;
ULONG Segment:16;
ULONG PrimaryBusNumber:8;
ULONG SecondaryBusNumber:8;
ULONG Reserved1:3;
ULONG SlotNumber:13; ULONG Reserved2:8;
} WHEA_PCIEXPRESS_DEVICE_ID, *PWHEA_PCIEXPRESS_DEVICE_ID;
typedef union _WHEA_PCIEXPRESS_BRIDGE_CONTROL_STATUS {
struct {
USHORT BridgeSecondaryStatus;
USHORT BridgeControl;
};
ULONG AsULONG;
} WHEA_PCIEXPRESS_BRIDGE_CONTROL_STATUS, *PWHEA_PCIEXPRESS_BRIDGE_CONTROL_STATUS;
typedef struct _WHEA_PCIEXPRESS_ERROR_SECTION {
WHEA_PCIEXPRESS_ERROR_SECTION_VALIDBITS ValidBits;
WHEA_PCIEXPRESS_DEVICE_TYPE PortType;
WHEA_PCIEXPRESS_VERSION Version;
WHEA_PCIEXPRESS_COMMAND_STATUS CommandStatus;
ULONG Reserved;
WHEA_PCIEXPRESS_DEVICE_ID DeviceId;
ULONGLONG DeviceSerialNumber;
WHEA_PCIEXPRESS_BRIDGE_CONTROL_STATUS BridgeControlStatus;
UCHAR ExpressCapability[60];
UCHAR AerInfo[96];
} WHEA_PCIEXPRESS_ERROR_SECTION, *PWHEA_PCIEXPRESS_ERROR_SECTION;
typedef union _WHEA_PCIXBUS_ERROR_SECTION_VALIDBITS {
struct {
ULONGLONG ErrorStatus :1;
ULONGLONG ErrorType :1;
ULONGLONG BusId :1;
ULONGLONG BusAddress :1;
ULONGLONG BusData :1;
ULONGLONG BusCommand :1;
ULONGLONG RequesterId :1;
ULONGLONG CompleterId :1;
ULONGLONG TargetId :1;
ULONGLONG Reserved :55;
};
ULONGLONG ValidBits;
} WHEA_PCIXBUS_ERROR_SECTION_VALIDBITS, *PWHEA_PCIXBUS_ERROR_SECTION_VALIDBITS;
typedef union _WHEA_PCIXBUS_ID {
struct {
UCHAR BusNumber;
UCHAR BusSegment;
};
USHORT AsUSHORT;
} WHEA_PCIXBUS_ID, *PWHEA_PCIXBUS_ID;
typedef union _WHEA_PCIXBUS_COMMAND {
struct {
ULONGLONG Command:56;
ULONGLONG PCIXCommand:1;
ULONGLONG Reserved:7;
};
ULONGLONG AsULONGLONG;
} WHEA_PCIXBUS_COMMAND, *PWHEA_PCIXBUS_COMMAND;
typedef struct _WHEA_PCIXBUS_ERROR_SECTION {
WHEA_PCIXBUS_ERROR_SECTION_VALIDBITS ValidBits;
WHEA_ERROR_STATUS ErrorStatus;
USHORT ErrorType;
WHEA_PCIXBUS_ID BusId;
ULONG Reserved;
ULONGLONG BusAddress;
ULONGLONG BusData;
WHEA_PCIXBUS_COMMAND BusCommand;
ULONGLONG RequesterId;
ULONGLONG CompleterId;
ULONGLONG TargetId;
} WHEA_PCIXBUS_ERROR_SECTION, *PWHEA_PCIXBUS_ERROR_SECTION;
typedef union _WHEA_PCIXDEVICE_ERROR_SECTION_VALIDBITS {
struct {
ULONGLONG ErrorStatus :1;
ULONGLONG IdInfo :1;
ULONGLONG MemoryNumber :1;
ULONGLONG IoNumber :1;
ULONGLONG RegisterDataPairs :1;
ULONGLONG Reserved :59;
};
ULONGLONG ValidBits;
} WHEA_PCIXDEVICE_ERROR_SECTION_VALIDBITS, *PWHEA_PCIXDEVICE_ERROR_SECTION_VALIDBITS;
typedef struct _WHEA_PCIXDEVICE_ID {
USHORT VendorId;
USHORT DeviceId;
ULONG ClassCode:24;
ULONG FunctionNumber:8;
ULONG DeviceNumber:8;
ULONG BusNumber:8;
ULONG SegmentNumber:8;
ULONG Reserved1:8;
ULONG Reserved2;
} WHEA_PCIXDEVICE_ID, *PWHEA_PCIXDEVICE_ID;
typedef struct WHEA_PCIXDEVICE_REGISTER_PAIR {
ULONGLONG Register;
ULONGLONG Data;
} WHEA_PCIXDEVICE_REGISTER_PAIR, *PWHEA_PCIXDEVICE_REGISTER_PAIR;
typedef struct _WHEA_PCIXDEVICE_ERROR_SECTION {
WHEA_PCIXDEVICE_ERROR_SECTION_VALIDBITS ValidBits;
WHEA_ERROR_STATUS ErrorStatus;
WHEA_PCIXDEVICE_ID IdInfo;
ULONG MemoryNumber;
ULONG IoNumber;
WHEA_PCIXDEVICE_REGISTER_PAIR RegisterDataPairs[ANYSIZE_ARRAY];
} WHEA_PCIXDEVICE_ERROR_SECTION, *PWHEA_PCIXDEVICE_ERROR_SECTION;
typedef enum _WHEA_RAW_DATA_FORMAT {
WheaRawDataFormatIPFSalRecord = 0x00,
WheaRawDataFormatIA32MCA,
WheaRawDataFormatIntel64MCA,
WheaRawDataFormatAMD64MCA,
WheaRawDataFormatMemory,
WheaRawDataFormatPCIExpress,
WheaRawDataFormatNMIPort,
WheaRawDataFormatPCIXBus,
WheaRawDataFormatPCIXDevice,
WheaRawDataFormatGeneric,
WheaRawDataFormatMax
} WHEA_RAW_DATA_FORMAT, *PWHEA_RAW_DATA_FORMAT;
typedef struct _WHEA_ERROR_PACKET_V1 {
ULONG Signature;
WHEA_ERROR_PACKET_FLAGS Flags;
ULONG Size;
ULONG RawDataLength;
ULONGLONG Reserved1;
ULONGLONG Context;
WHEA_ERROR_TYPE ErrorType;
WHEA_ERROR_SEVERITY ErrorSeverity;
ULONG ErrorSourceId;
WHEA_ERROR_SOURCE_TYPE ErrorSourceType;
ULONG Reserved2;
ULONG Version;
ULONGLONG Cpu;
union {
WHEA_PROCESSOR_GENERIC_ERROR_SECTION ProcessorError;
WHEA_MEMORY_ERROR_SECTION MemoryError;
WHEA_NMI_ERROR_SECTION NmiError;
WHEA_PCIEXPRESS_ERROR_SECTION PciExpressError;
WHEA_PCIXBUS_ERROR_SECTION PciXBusError;
WHEA_PCIXDEVICE_ERROR_SECTION PciXDeviceError;
} u;
WHEA_RAW_DATA_FORMAT RawDataFormat;
ULONG RawDataOffset;
UCHAR RawData[1];
} WHEA_ERROR_PACKET_V1, *PWHEA_ERROR_PACKET_V1;