Usually, the parameter 1 = 0 of BSOD 0x124, then the parameter 2 is the address of the WHEA_ERROR_RECORD structure. http://msdn.microsoft.com/en-us/library/windows/hardware/ff560483(v=vs.85).aspx
Below is the detail information for the data structure information.
typedef struct _WHEA_ERROR_RECORD { WHEA_ERROR_RECORD_HEADER Header; WHEA_ERROR_RECORD_SECTION_DESCRIPTOR SectionDescriptor[ANYSIZE_ARRAY]; } WHEA_ERROR_RECORD, *PWHEA_ERROR_RECORD;
typedef struct _WHEA_ERROR_RECORD_HEADER { ULONG Signature; WHEA_REVISION Revision; ULONG SignatureEnd; USHORT SectionCount; WHEA_ERROR_SEVERITY Severity; WHEA_ERROR_RECORD_HEADER_VALIDBITS ValidBits; ULONG Length; WHEA_TIMESTAMP Timestamp; GUID PlatformId; GUID PartitionId; GUID CreatorId; GUID NotifyType; ULONGLONG RecordId; WHEA_ERROR_RECORD_HEADER_FLAGS Flags; WHEA_PERSISTENCE_INFO PersistenceInfo; UCHAR Reserved[12]; } WHEA_ERROR_RECORD_HEADER, *PWHEA_ERROR_RECORD_HEADER;
Signature = 'REPC'typedef union _WHEA_REVISION { struct { UCHAR MinorRevision; UCHAR MajorRevision; }; USHORT AsUSHORT; } WHEA_REVISION, *PWHEA_REVISION;typedef enum _WHEA_ERROR_SEVERITY { WheaErrSevRecoverable = 0, WheaErrSevFatal = 1, WheaErrSevCorrected = 2, WheaErrSevInformational = 3 } WHEA_ERROR_SEVERITY, *PWHEA_ERROR_SEVERITY;typedef union _WHEA_ERROR_RECORD_HEADER_VALIDBITS { struct { ULONG PlatformId :1; ULONG Timestamp :1; ULONG PartitionId :1; ULONG Reserved :29; }; ULONG AsULONG; } WHEA_ERROR_RECORD_HEADER_VALIDBITS, *PWHEA_ERROR_RECORD_HEADER_VALIDBITS;Length = The length, in bytes, of the error record.
typedef union _WHEA_TIMESTAMP { struct { ULONGLONG Seconds :8; ULONGLONG Minutes :8; ULONGLONG Hours :8; ULONGLONG Precise :1; ULONGLONG Reserved :7; ULONGLONG Day :8; ULONGLONG Month :8; ULONGLONG Year :8; ULONGLONG Century :8; }; LARGE_INTEGER AsLARGE_INTEGER; } WHEA_TIMESTAMP, *PWHEA_TIMESTAMP;typedef union _WHEA_ERROR_RECORD_HEADER_FLAGS { struct { ULONG Recovered:1; ULONG PreviousError:1; ULONG Simulated:1; ULONG Reserved:29; }; ULONG AsULONG; } WHEA_ERROR_RECORD_HEADER_FLAGS, *PWHEA_ERROR_RECORD_HEADER_FLAGS;typedef union _WHEA_PERSISTENCE_INFO { struct { ULONGLONG Signature :16; ULONGLONG Length :24; ULONGLONG Identifier :16; ULONGLONG Attributes :2; ULONGLONG DoNotLog :1; ULONGLONG Reserved :5; }; ULONGLONG AsULONGLONG; } WHEA_PERSISTENCE_INFO, *PWHEA_PERSISTENCE_INFO;//--------------------------------------------------------------------------------------typedef struct _WHEA_ERROR_RECORD_SECTION_DESCRIPTOR { ULONG SectionOffset; ULONG SectionLength; WHEA_REVISION Revision; WHEA_ERROR_RECORD_SECTION_DESCRIPTOR_VALIDBITS ValidBits; UCHAR Reserved; WHEA_ERROR_RECORD_SECTION_DESCRIPTOR_FLAGS Flags; GUID SectionType; GUID FRUId; WHEA_ERROR_SEVERITY SectionSeverity; CCHAR FRUText[20]; } WHEA_ERROR_RECORD_SECTION_DESCRIPTOR, *PWHEA_ERROR_RECORD_SECTION_DESCRIPTOR;typedef union _WHEA_ERROR_RECORD_SECTION_DESCRIPTOR_VALIDBITS { struct { UCHAR FRUId :1; UCHAR FRUText :1; UCHAR Reserved :6; }; UCHAR AsUCHAR; } WHEA_ERROR_RECORD_SECTION_DESCRIPTOR_VALIDBITS, *PWHEA_ERROR_RECORD_SECTION_DESCRIPTOR_VALIDBITS;
typedef union _WHEA_ERROR_RECORD_SECTION_DESCRIPTOR_FLAGS { struct { ULONG Primary:1; ULONG ContainmentWarning:1; ULONG Reset:1; ULONG ThresholdExceeded:1; ULONG ResourceNotAvailable:1; ULONG LatentError:1; ULONG Reserved:26; }; ULONG AsULONG; } WHEA_ERROR_RECORD_SECTION_DESCRIPTOR_FLAGS, *PWHEA_ERROR_RECORD_SECTION_DESCRIPTOR_FLAGS;//////////////////////////////////////////////////////////////////////////////////////////////////
typedef struct _WHEA_PROCESSOR_GENERIC_ERROR_SECTION { WHEA_PROCESSOR_GENERIC_ERROR_SECTION_VALIDBITS ValidBits; UCHAR ProcessorType; UCHAR InstructionSet; UCHAR ErrorType; UCHAR Operation; UCHAR Flags; UCHAR Level; USHORT Reserved; ULONGLONG CPUVersion; UCHAR CPUBrandString[128]; ULONGLONG ProcessorId; ULONGLONG TargetAddress; ULONGLONG RequesterId; ULONGLONG ResponderId; ULONGLONG InstructionPointer; } WHEA_PROCESSOR_GENERIC_ERROR_SECTION, *PWHEA_PROCESSOR_GENERIC_ERROR_SECTION;
typedef union _WHEA_PROCESSOR_GENERIC_ERROR_SECTION_VALIDBITS { struct { ULONGLONG ProcessorType :1; ULONGLONG InstructionSet :1; ULONGLONG ErrorType :1; ULONGLONG Operation :1; ULONGLONG Flags :1; ULONGLONG Level :1; ULONGLONG CPUVersion :1; ULONGLONG CPUBrandString :1; ULONGLONG ProcessorId :1; ULONGLONG TargetAddress :1; ULONGLONG RequesterId :1; ULONGLONG ResponderId :1; ULONGLONG InstructionPointer :1; ULONGLONG Reserved :51; }; ULONGLONG ValidBits; } WHEA_PROCESSOR_GENERIC_ERROR_SECTION_VALIDBITS, *PWHEA_PROCESSOR_GENERIC_ERROR_SECTION_VALIDBITS;
#define WHEA_ERROR_PACKET_V1_SIGNATURE 'tPrE'
#define WHEA_ERROR_PACKET_V1_VERSION 2
#define WHEA_ERROR_PACKET_V2_SIGNATURE 'AEHW'
#define WHEA_ERROR_PACKET_V2_VERSION 3
typedef union _WHEA_ERROR_PACKET_FLAGS {
struct {
ULONG PreviousError :1;
ULONG Reserved1 :1;
ULONG HypervisorError :1;
ULONG Simulated :1;
ULONG PlatformPfaControl :1;
ULONG PlatformDirectedOffline :1;
ULONG Reserved2 :26;
};
ULONG AsULONG;
} WHEA_ERROR_PACKET_FLAGS, *PWHEA_ERROR_PACKET_FLAGS;
typedef enum _WHEA_ERROR_TYPE {
WheaErrTypeProcessor = 0,
WheaErrTypeMemory,
WheaErrTypePCIExpress,
WheaErrTypeNMI,
WheaErrTypePCIXBus,
WheaErrTypePCIXDevice,
WheaErrTypeGeneric
} WHEA_ERROR_TYPE, *PWHEA_ERROR_TYPE;
typedef enum _WHEA_ERROR_SOURCE_TYPE {
WheaErrSrcTypeMCE = 0x00,
WheaErrSrcTypeCMC = 0x01,
WheaErrSrcTypeCPE = 0x02,
WheaErrSrcTypeNMI = 0x03,
WheaErrSrcTypePCIe = 0x04,
WheaErrSrcTypeGeneric = 0x05,
WheaErrSrcTypeINIT = 0x06,
WheaErrSrcTypeBOOT = 0x07,
WheaErrSrcTypeSCIGeneric = 0x08,
WheaErrSrcTypeIPFMCA = 0x09,
WheaErrSrcTypeIPFCMC = 0x0a,
WheaErrSrcTypeIPFCPE = 0x0b,
WheaErrSrcTypeMax
} WHEA_ERROR_SOURCE_TYPE, *PWHEA_ERROR_SOURCE_TYPE;
typedef enum _WHEA_ERROR_PACKET_DATA_FORMAT {
WheaDataFormatIPFSalRecord = 0,
WheaDataFormatXPFMCA,
WheaDataFormatMemory,
WheaDataFormatPCIExpress,
WheaDataFormatNMIPort,
WheaDataFormatPCIXBus,
WheaDataFormatPCIXDevice,
WheaDataFormatGeneric,
WheaDataFormatMax
} WHEA_ERROR_PACKET_DATA_FORMAT, *PWHEA_ERROR_PACKET_DATA_FORMAT;
typedef union _WHEA_MEMORY_ERROR_SECTION_VALIDBITS {
struct {
ULONGLONG ErrorStatus :1;
ULONGLONG PhysicalAddress :1;
ULONGLONG PhysicalAddressMask :1;
ULONGLONG Node :1;
ULONGLONG Card :1;
ULONGLONG Module :1;
ULONGLONG Bank :1;
ULONGLONG Device :1;
ULONGLONG Row :1;
ULONGLONG Column :1;
ULONGLONG BitPosition :1;
ULONGLONG RequesterId :1;
ULONGLONG ResponderId :1;
ULONGLONG TargetId :1;
ULONGLONG ErrorType :1;
ULONGLONG Reserved :49;
};
ULONGLONG ValidBits;
} WHEA_MEMORY_ERROR_SECTION_VALIDBITS, *PWHEA_MEMORY_ERROR_SECTION_VALIDBITS;
typedef union _WHEA_ERROR_STATUS {
ULONGLONG ErrorStatus;
struct {
ULONGLONG Reserved1 :8;
ULONGLONG ErrorType :8;
ULONGLONG Address :1;
ULONGLONG Control :1;
ULONGLONG Data :1;
ULONGLONG Responder :1;
ULONGLONG Requester :1;
ULONGLONG FirstError :1;
ULONGLONG Overflow :1;
ULONGLONG Reserved2 :41;
};
} WHEA_ERROR_STATUS, *PWHEA_ERROR_STATUS;
typedef struct _WHEA_MEMORY_ERROR_SECTION {
WHEA_MEMORY_ERROR_SECTION_VALIDBITS ValidBits;
WHEA_ERROR_STATUS ErrorStatus;
ULONGLONG PhysicalAddress;
ULONGLONG PhysicalAddressMask;
USHORT Node;
USHORT Card;
USHORT Module;
USHORT Bank;
USHORT Device;
USHORT Row;
USHORT Column;
USHORT BitPosition;
ULONGLONG RequesterId;
ULONGLONG ResponderId;
ULONGLONG TargetId;
UCHAR ErrorType;
} WHEA_MEMORY_ERROR_SECTION, *PWHEA_MEMORY_ERROR_SECTION;
typedef union _WHEA_NMI_ERROR_SECTION_FLAGS {
struct {
ULONG HypervisorError:1;
ULONG Reserved:31;
};
ULONG AsULONG;
} WHEA_NMI_ERROR_SECTION_FLAGS, *PWHEA_NMI_ERROR_SECTION_FLAGS;
typedef struct _WHEA_NMI_ERROR_SECTION {
UCHAR Data[8];
WHEA_NMI_ERROR_SECTION_FLAGS Flags;
} WHEA_NMI_ERROR_SECTION, *PWHEA_NMI_ERROR_SECTION;
typedef union _WHEA_PCIEXPRESS_ERROR_SECTION_VALIDBITS {
struct {
ULONGLONG PortType :1;
ULONGLONG Version :1;
ULONGLONG CommandStatus :1;
ULONGLONG DeviceId :1;
ULONGLONG DeviceSerialNumber :1;
ULONGLONG BridgeControlStatus :1;
ULONGLONG ExpressCapability :1;
ULONGLONG AerInfo :1;
ULONGLONG Reserved :56;
};
ULONGLONG ValidBits;
} WHEA_PCIEXPRESS_ERROR_SECTION_VALIDBITS, *PWHEA_PCIEXPRESS_ERROR_SECTION_VALIDBITS;
typedef enum {
WheaPciExpressEndpoint = 0,
WheaPciExpressLegacyEndpoint,
WheaPciExpressRootPort = 4,
WheaPciExpressUpstreamSwitchPort,
WheaPciExpressDownstreamSwitchPort,
WheaPciExpressToPciXBridge,
WheaPciXToExpressBridge,
WheaPciExpressRootComplexIntegratedEndpoint,
WheaPciExpressRootComplexEventCollector
} WHEA_PCIEXPRESS_DEVICE_TYPE;
typedef union _WHEA_PCIEXPRESS_VERSION {
struct {
UCHAR MinorVersion;
UCHAR MajorVersion;
USHORT Reserved;
};
ULONG AsULONG;
} WHEA_PCIEXPRESS_VERSION, *PWHEA_PCIEXPRESS_VERSION;
typedef union _WHEA_PCIEXPRESS_COMMAND_STATUS {
struct {
USHORT Command;
USHORT Status;
};
ULONG AsULONG;
} WHEA_PCIEXPRESS_COMMAND_STATUS, *PWHEA_PCIEXPRESS_COMMAND_STATUS;
typedef struct _WHEA_PCIEXPRESS_DEVICE_ID {
USHORT VendorID;
USHORT DeviceID;
ULONG ClassCode:24;
ULONG FunctionNumber:8;
ULONG DeviceNumber:8;
ULONG Segment:16;
ULONG PrimaryBusNumber:8;
ULONG SecondaryBusNumber:8;
ULONG Reserved1:3;
ULONG SlotNumber:13; ULONG Reserved2:8;
} WHEA_PCIEXPRESS_DEVICE_ID, *PWHEA_PCIEXPRESS_DEVICE_ID;
typedef union _WHEA_PCIEXPRESS_BRIDGE_CONTROL_STATUS {
struct {
USHORT BridgeSecondaryStatus;
USHORT BridgeControl;
};
ULONG AsULONG;
} WHEA_PCIEXPRESS_BRIDGE_CONTROL_STATUS, *PWHEA_PCIEXPRESS_BRIDGE_CONTROL_STATUS;
typedef struct _WHEA_PCIEXPRESS_ERROR_SECTION {
WHEA_PCIEXPRESS_ERROR_SECTION_VALIDBITS ValidBits;
WHEA_PCIEXPRESS_DEVICE_TYPE PortType;
WHEA_PCIEXPRESS_VERSION Version;
WHEA_PCIEXPRESS_COMMAND_STATUS CommandStatus;
ULONG Reserved;
WHEA_PCIEXPRESS_DEVICE_ID DeviceId;
ULONGLONG DeviceSerialNumber;
WHEA_PCIEXPRESS_BRIDGE_CONTROL_STATUS BridgeControlStatus;
UCHAR ExpressCapability[60];
UCHAR AerInfo[96];
} WHEA_PCIEXPRESS_ERROR_SECTION, *PWHEA_PCIEXPRESS_ERROR_SECTION;
typedef union _WHEA_PCIXBUS_ERROR_SECTION_VALIDBITS {
struct {
ULONGLONG ErrorStatus :1;
ULONGLONG ErrorType :1;
ULONGLONG BusId :1;
ULONGLONG BusAddress :1;
ULONGLONG BusData :1;
ULONGLONG BusCommand :1;
ULONGLONG RequesterId :1;
ULONGLONG CompleterId :1;
ULONGLONG TargetId :1;
ULONGLONG Reserved :55;
};
ULONGLONG ValidBits;
} WHEA_PCIXBUS_ERROR_SECTION_VALIDBITS, *PWHEA_PCIXBUS_ERROR_SECTION_VALIDBITS;
typedef union _WHEA_PCIXBUS_ID {
struct {
UCHAR BusNumber;
UCHAR BusSegment;
};
USHORT AsUSHORT;
} WHEA_PCIXBUS_ID, *PWHEA_PCIXBUS_ID;
typedef union _WHEA_PCIXBUS_COMMAND {
struct {
ULONGLONG Command:56;
ULONGLONG PCIXCommand:1;
ULONGLONG Reserved:7;
};
ULONGLONG AsULONGLONG;
} WHEA_PCIXBUS_COMMAND, *PWHEA_PCIXBUS_COMMAND;
typedef struct _WHEA_PCIXBUS_ERROR_SECTION {
WHEA_PCIXBUS_ERROR_SECTION_VALIDBITS ValidBits;
WHEA_ERROR_STATUS ErrorStatus;
USHORT ErrorType;
WHEA_PCIXBUS_ID BusId;
ULONG Reserved;
ULONGLONG BusAddress;
ULONGLONG BusData;
WHEA_PCIXBUS_COMMAND BusCommand;
ULONGLONG RequesterId;
ULONGLONG CompleterId;
ULONGLONG TargetId;
} WHEA_PCIXBUS_ERROR_SECTION, *PWHEA_PCIXBUS_ERROR_SECTION;
typedef union _WHEA_PCIXDEVICE_ERROR_SECTION_VALIDBITS {
struct {
ULONGLONG ErrorStatus :1;
ULONGLONG IdInfo :1;
ULONGLONG MemoryNumber :1;
ULONGLONG IoNumber :1;
ULONGLONG RegisterDataPairs :1;
ULONGLONG Reserved :59;
};
ULONGLONG ValidBits;
} WHEA_PCIXDEVICE_ERROR_SECTION_VALIDBITS, *PWHEA_PCIXDEVICE_ERROR_SECTION_VALIDBITS;
typedef struct _WHEA_PCIXDEVICE_ID {
USHORT VendorId;
USHORT DeviceId;
ULONG ClassCode:24;
ULONG FunctionNumber:8;
ULONG DeviceNumber:8;
ULONG BusNumber:8;
ULONG SegmentNumber:8;
ULONG Reserved1:8;
ULONG Reserved2;
} WHEA_PCIXDEVICE_ID, *PWHEA_PCIXDEVICE_ID;
typedef struct WHEA_PCIXDEVICE_REGISTER_PAIR {
ULONGLONG Register;
ULONGLONG Data;
} WHEA_PCIXDEVICE_REGISTER_PAIR, *PWHEA_PCIXDEVICE_REGISTER_PAIR;
typedef struct _WHEA_PCIXDEVICE_ERROR_SECTION {
WHEA_PCIXDEVICE_ERROR_SECTION_VALIDBITS ValidBits;
WHEA_ERROR_STATUS ErrorStatus;
WHEA_PCIXDEVICE_ID IdInfo;
ULONG MemoryNumber;
ULONG IoNumber;
WHEA_PCIXDEVICE_REGISTER_PAIR RegisterDataPairs[ANYSIZE_ARRAY];
} WHEA_PCIXDEVICE_ERROR_SECTION, *PWHEA_PCIXDEVICE_ERROR_SECTION;
typedef enum _WHEA_RAW_DATA_FORMAT {
WheaRawDataFormatIPFSalRecord = 0x00,
WheaRawDataFormatIA32MCA,
WheaRawDataFormatIntel64MCA,
WheaRawDataFormatAMD64MCA,
WheaRawDataFormatMemory,
WheaRawDataFormatPCIExpress,
WheaRawDataFormatNMIPort,
WheaRawDataFormatPCIXBus,
WheaRawDataFormatPCIXDevice,
WheaRawDataFormatGeneric,
WheaRawDataFormatMax
} WHEA_RAW_DATA_FORMAT, *PWHEA_RAW_DATA_FORMAT;
typedef struct _WHEA_ERROR_PACKET_V1 {
ULONG Signature;
WHEA_ERROR_PACKET_FLAGS Flags;
ULONG Size;
ULONG RawDataLength;
ULONGLONG Reserved1;
ULONGLONG Context;
WHEA_ERROR_TYPE ErrorType;
WHEA_ERROR_SEVERITY ErrorSeverity;
ULONG ErrorSourceId;
WHEA_ERROR_SOURCE_TYPE ErrorSourceType;
ULONG Reserved2;
ULONG Version;
ULONGLONG Cpu;
union {
WHEA_PROCESSOR_GENERIC_ERROR_SECTION ProcessorError;
WHEA_MEMORY_ERROR_SECTION MemoryError;
WHEA_NMI_ERROR_SECTION NmiError;
WHEA_PCIEXPRESS_ERROR_SECTION PciExpressError;
WHEA_PCIXBUS_ERROR_SECTION PciXBusError;
WHEA_PCIXDEVICE_ERROR_SECTION PciXDeviceError;
} u;
WHEA_RAW_DATA_FORMAT RawDataFormat;
ULONG RawDataOffset;
UCHAR RawData[1];
} WHEA_ERROR_PACKET_V1, *PWHEA_ERROR_PACKET_V1;
typedef struct _WHEA_ERROR_PACKET_V2 {
ULONG Signature;
ULONG Version;
ULONG Length;
WHEA_ERROR_PACKET_FLAGS Flags;
WHEA_ERROR_TYPE ErrorType;
WHEA_ERROR_SEVERITY ErrorSeverity;
ULONG ErrorSourceId;
WHEA_ERROR_SOURCE_TYPE ErrorSourceType;
GUID NotifyType;
ULONGLONG Context;
WHEA_ERROR_PACKET_DATA_FORMAT DataFormat;
ULONG Reserved1;
ULONG DataOffset;
ULONG DataLength;
ULONG PshedDataOffset;
ULONG PshedDataLength;
} WHEA_ERROR_PACKET_V2, *PWHEA_ERROR_PACKET_V2;
typedef union _MCI_STATS {
struct {
USHORT McaCod;
USHORT MsCod;
ULONG OtherInfo : 25;
ULONG Damage : 1;
ULONG AddressValid : 1;
ULONG MiscValid : 1;
ULONG Enabled : 1;
ULONG UnCorrected : 1;
ULONG OverFlow : 1;
ULONG Valid : 1;
} MciStats;
ULONGLONG QuadPart;
} MCI_STATS, *PMCI_STATS;
typedef union _MCI_ADDR{
struct {
ULONG Address;
ULONG Reserved;
} MciAddr;
ULONGLONG QuadPart;
} MCI_ADDR, *PMCI_ADDR;
typedef enum
{
HAL_MCE_RECORD = 0,
HAL_MCA_RECORD = 1
} MCA_EXCEPTION_TYPE;
typedef struct _MCA_EXCEPTION {
ULONG VersionNumber; // Version number of this record type
MCA_EXCEPTION_TYPE ExceptionType; // MCA or MCE
LARGE_INTEGER TimeStamp; // exception recording timestamp
ULONG ProcessorNumber;// processor number
union {
struct {
UCHAR BankNumber; // bank number
MCI_STATS Status;
MCI_ADDR Address;
ULONGLONG Misc;
} Mca;
struct {
ULONGLONG McAddress; // physical address for the cycle causing the error
ULONGLONG McType; // cycle specification causing the error
} Mce;
} u;
} MCA_EXCEPTION, *PMCA_EXCEPTION;
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